A data storage device such as a magnetic, optical, or magneto-optical drive includes several main electronic components such as a read/write channel chip, a differential preamplifier, and a main controller incorporating a microprocessor. Firmware code stored in memory, either external or internal to the microprocessor, and executed by the microprocessor controls the behavior of the components of the data storage device. Additionally, registers maintained in the memory store values used by the firmware code to control the individual components. That is, the behavior of the components of the data storage device may be controlled in part by the values set in these registers. Included in these register values may be a set of permanent Power-On-Reset (POR) register values that are loaded into the registers of the various components by a start-up routine executed every time power is applied to the data storage device.
During the initial stages of drive development, the firmware codes and POR register values are saved in an external Read-Only Memory (ROM) such as a flash ROM. Code used during power up of the data storage device such as a start-up routine and a set of default POR register values can be programmed into the flash ROM as needed. The flash ROM is helpful because the ROM codes and POR register values are constantly changing during the initial stages of drive development. However, as the design matures, the code and POR values are fixed and seldom change. Therefore, an economical way to store this data is to integrate it into a piece of hardware such as the internal ROM of the microprocessor. Apart from saving cost, saving the code and POR values in ROM will also reduce processing time during certification testing of the data storage device by eliminating ROM code from the list of files that are downloaded into the drive during the certification process.
Certification of the data storage device typically takes place after the data storage device has completed or nearly completed the manufacturing process. The certification process may involve tests of a variety of parameters related to performance of the data storage device to determine whether the device will be suitable for its potential uses. For example, certification testing may include a time-to-ready test that determines whether the data storage device is able to start up within an amount of time acceptable to users of the device.
The POR register values stored in the ROM are typically mean values obtained from a large population of drives that had passed certification testing in the initial development phase. Therefore, the POR register values are determined based on the assumption that a generic set of POR register values should work for the majority of drives.
However, problems arise when the POR register values are not tuned for some drives. That is, the generic set of POR register values stored in the ROM is not appropriate for some drives. One reason a generic set of POR register values may not work well in all registers is the fact the some of these registers are used to store values used to counter drift or set gain, offset, etc in analog circuits. Therefore, there may be a big difference between the generic POR register values stored in the ROM and appropriate POR register values for some circuits in some drives.
As a result, these drives may experience a large number of read retries and require a much longer time to boot-up. These drives may therefore fail in a time-to-ready test that may be part of the certification process and cause a significant process yield problem. However, these drives may not be physically faulty and may even perform well with register values that are tuned to that specific drive.
However, since it is a read-only memory, the ROM is generally unchangeable once it has been set. Accordingly there is a need for a method of patching specific registers with tuned values at an early stage of the start-up routine. The present invention provides a solution to this and other problems, and offers other advantages over the prior art.